The invention relates to a circuit arrangement for supplying configuration data in FPGA devices.
FPGAs (field programmable gate arrays) are integrated electronic circuits which are completely programmable by the user (“in the field”) and perform a multiplicity of logic functions desired by the user in accordance with their programming or their configuration, respectively. As a rule, configurable logic blocks and configurable wiring resources are provided for this purpose in an FPGA, the electrical interconnections of these with one another being determined by a multiplicity of switches which can be set by configuration bits. The logic functions of the configurable logic blocks, which, in turn, are configured of configurable logic cells, are also specified by configuration bits. The configuration or programming of an FPGA is thus performed by the writing-in and (volatile) storing of corresponding configuration data in memories kept available in the logic blocks. Thus, a complex logic chip is formed overall.
A number of logic cells and their associated wiring resources, that is to say prefabricated electrical connecting elements definable by the configuration bits, are combined as a configurable logic block or as a logic page. A corresponding logic page also exhibits a local configuration memory in which the required configuration bits are stored. In the text which follows, individual logic cells with configuration shift registers are mentioned in a simplified manner as local configuration memories.
Before an FPGA starts to operate, all configuration bits must be written into the local configuration memories from the outside. This must be done after each new start-up after the voltage supply has been switched off. However, it is frequently desired to keep the configuration data available in a nonvolatile manner in a memory integrated in the corresponding FPGA chip. In this case, the configuration data only need to be transported from the nonvolatile memory into the local configuration memory.
A so-called nonvolatile FPGA chip therefore has as basic elements the configurable logic cells mentioned initially and additionally a nonvolatile memory for storing configuration data. In this configuration memory, for example, the corresponding configuration bits are stored in suitably structured form “in the field” and when the FPGA is started up, they are first supplied as configuration bits to the settable switches present in the configurable cells. A respective configurable logic cell therefore has a configuration register which stores a respective configuration word of configuration bits in a volatile manner for the operation of the FPGA and individually provides the configuration bits which lastly determine the logic function of the configurable logic cell.
The configurable logic cells and the local configuration memory are typically implemented in the same production technology, for example CMOS, whereas the non-volatile configuration memory needs another technology, e.g. FLASH. For the circuit sections constructed in different technologies, different signal levels are then used. Matching the corresponding logic levels then increases the circuit expenditure.
A special feature in nonvolatile configuration memories is the verification of the configuration data written in. This can be done by reading out the information written in and comparing with the written data. This verification method can disadvantageously require a number of cycles.
FIG. 1 shows by way of example the structure of a configurable logic cell LC for conventional FPGAs as disclosed, for example, in published European application for patent EP 1 324 495 A1.
A correspondingly configurable logic cell LC is used for converting a logic function which receives the input data PD and outputs a corresponding logically combined result FFO. A configuration shift register CM is provided which stores configuration bits CB and provides them to the input of a first multiplexer MUX1. The first multiplexer MUX1 defines one of the configuration bits CB as output signal LTO in dependence on the input data PD. The multiplexer MUX1 with the configuration bits CB supplied by the configuration shift register CM can be understood to be a look up table LUT. It is possible, therefore, to perform a Boolean function with the input data PD as input variables and the output signals LTO of the multiplexer or the look up table LUT, respectively.
Furthermore, a D-type flip flop DFF with a data input D, a data output Q and a clock input CK is provided. The output signal LTO of the look up table is conducted to the data input D and a clock signal CLK1 is applied to the clock input CK. The output signal LTO of the look up table LUT is also conducted to an input of a second multiplexer MUX2 which also receives the output signal FFO of the D-type flip flop DFF. The second multiplexer MUX2 switches through either the output signal FFO of the flip flop DFF or the output signal LTO of the look up table LUT as output signal FFO′ of the configurable logic cell LC in dependence on one of the configuration bits CB′. If FPGA chips are used for applications in data processing, the clocked output signals FFO of the D-type flip flop DFF which, as a rule, is provided in a configurable logic cell LC for an FPGA chip, and in most cases used. The D-type flip flop DFF is then used for temporarily storing the output signal of the logic cell LC.
In FIG. 2 the basic elements of a conventional nonvolatile FPGA chip FPGA are shown diagrammatically.
The FPGA has configurable logic cells LC1, LC2, LCN in a column, wherein each configurable logic cell supplies a respective logic result FF0, FF1, FFN from the respect input signals PD1, PD2, PD3 to an output A1, A2, AN. The configurable logic cells LC1, LC2, LCN in each case have configuration shift registers CM1, CM2, CMN for storing and providing configuration bits for the respective logic cell LC1, LC2, LCN.
Before the FPGA starts up, in a configuration phase, the respective configuration bits are read out of a nonvolatile memory MCA as serial configuration data SCD1, SCD2, SCDN into the configuration shift registers CM1, CM2, CMN. The configuration memory MCA can have, for example, a memory cell array of nonvolatile memory elements such as, for example, MRAM or FRAM memory cells. The actual programming of the FPGA takes place in a read-in phase in which the configuration data are written into the memory cell array MCA. For this purpose, a further loading shift register ISR is provided, with a number N of shift register cells Z1, Z2, ZN which corresponds to the number of the bit lines BL1, . . . BLN coupled to the memory cell array MCA of nonvolatile memory elements.
The configuration data CD are read serially into this loading shift register ISR clock cycle by clock cycle with a clock CLK. Each of these shift register cells Z1, Z2, ZN is coupled to a bit line BL1, BL2, BLN. The respective bit lines BL1, BL2, BLN of the memory cell array MCA are crossed with word lines WL1, WL2, WLN, the number of word lines corresponding to the number of respective configuration bits for a configurable logic cell LC1. In the writing-in phase of the configuration data CD, all first configuration bits for the configurable logic cells LC1, LC2, LCN are first serially written into the nonvolatile memory cells NVMC. In a further step, second configuration bits are written until all configuration data CD are conducted into the memory cell array MCA. It is only then that the configuration shift registers CM1, CM2, CMN, with closed controllable switches SW1, SW2, SWN, are filled with the configuration bits stored in the nonvolatile memory cells NVMC of a respective bit line BL1, BL2, BLN in the configuration phase of the FPGA.
With an embodiment of the nonvolatile memory cells NVMC as FRAM cells, in particular, additional elaborate converter circuits, which are not shown here, are required for reading and writing the memory cell contents. A disadvantage of the solution in shown in FIG. 2 for writing configuration data CD into the nonvolatile memory MCA via a shift register ISR is also the additional wiring expenditure due to the coupling of the individual shift register cells Z1, Z2, ZN of the loading shift register ISR to the bit lines BL1, BL2, BLN and the increased circuit expenditure due to the shift register ISR itself.